Semiconductor devices are susceptible to damage from electrostatic discharge (ESD) events. ESD events may produce voltage overstress on components such as metal oxide semiconductor (MOS) transistors, resulting in failure or reduced reliability of the components. Signal pads of semiconductor devices are commonly connected to internal power and ground lines through diodes which are reverse biased during normal operation. The diodes provide conductive paths from the signal pads to the power and ground lines during ESD events, thus reducing the damaging effects of the voltage overstress on components connected to the signal pads. Voltage clamps are commonly connected between the power and ground lines, to reduce voltage transients during ESD events. An effective clamp includes a trigger circuit with a resistor-capacitor (RC) low-pass filter connected to a source follower. The trigger circuit drives a clamp MOS transistor connected between the power and ground lines. A limitation of this voltage clamp is exhibited during two or more ESD events in rapid succession: charge builds up on the power line, and does not sufficiently dissipate before the next ESD event, inhibiting timely triggering of the source follower, resulting in voltage overstress on components connected to the power line.